Miller Effect Mitigation
Miller Effect Mitigation is a gate drive circuit technique that reduces the unintended turn-on of power transistors by minimizing the capacitive coupling between gate and drain terminals during high-speed switching transitions.
36
Publications
1K
Citations
131
Authors
46
Institutions
Publications per year
2017–2026
13
Parents
36
1–5 of 36
131
2
h-index
2
h-index
2
h-index
2
h-index
2
h-index
1–5 of 131
46
Fuji Electric (Japan)
Tokyo, Japan
3 h-index
14 publications
419 citations
University of Florida
Gainesville, United States
2 h-index
4 publications
78 citations

University of Electronic Science and Technology of China
Chengdu, China
2 h-index
8 publications
115 citations
Hitachi (Japan)
Tokyo, Japan
2 h-index
6 publications
211 citations
Motorola (United States)
Schaumburg, United States
2 h-index
3 publications
42 citations

Hefei University of Technology
Hefei, China
1 h-index
4 publications
60 citations
University of California, Los Angeles
Los Angeles, United States
1 h-index
3 publications
78 citations
Ingenieurgesellschaft Auto und Verkehr (Germany)
Berlin, Germany
1 h-index
3 publications
105 citations
1–8 of 46
4 publications · 188 citations
4
h-index
3 publications · 85 citations
3
h-index
2 publications · 42 citations
2
h-index
1 publications · 18 citations
1
h-index
1 publications · 37 citations
1
h-index
1–5