Miller Effect Mitigation

Miller Effect Mitigation is a gate drive circuit technique that reduces the unintended turn-on of power transistors by minimizing the capacitive coupling between gate and drain terminals during high-speed switching transitions.

36

Publications

1K

Citations

131

Authors

46

Institutions

Publications per year

2017–2026

13

Authors

131

  1. RD
    R.W. Dutton

    Stanford University, United States

    2 publications · 112 citations

    2

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  2. YI
    Yoshihiro Ikura

    Fuji Electric (Japan), Japan

    2 publications · 61 citations

    2

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  3. SW
    Shuo Wang

    University of Florida, United States

    2 publications · 39 citations

    2

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  4. KO
    Kota Ohi

    Fuji Electric (Japan), Japan

    2 publications · 61 citations

    2

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  5. RC
    R. Chokhawala

    Motorola (United States), United States

    2 publications · 26 citations

    2

    h-index

1–5 of 131

Venues

  1. IEEE Transactions on Power Electronics

    4 publications · 188 citations

    4

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  2. 3

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  3. IEEE Transactions on Electron Devices

    2 publications · 42 citations

    2

    h-index

  4. ETRI Journal

    1 publications · 18 citations

    1

    h-index

  5. 1

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1–5