Low-Power Data Cache Design is a specialized methodology within computer architecture that focuses on minimizing energy consumption in data cache subsystems through optimized circuit, organization, and access techniques while maintaining performance and capacity constraints.
120
Publications
4.7K
Citations
513
Authors
100
Institutions
Publications per year
2017–2026
7
Parents
Publications
120
Dynamic zero compression for cache energy reduction
Luís Villa, Michael Zhang, Krste Asanović · 2000 · 195 citations
1–5 of 120
Authors
513
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1–5 of 513
Institutions
100
Intel (United States)
Santa Clara, United States
18 h-index
123 publications
5.8K citations
University of California, Irvine
Irvine, United States
6 h-index
18 publications
400 citations
IBM (United States)
Armonk, United States
5 h-index
46 publications
911 citations
Pennsylvania State University
State College, United States
5 h-index
14 publications
340 citations
Universitat Politècnica de Catalunya
Barcelona, Spain
4 h-index
12 publications
208 citations
Purdue University West Lafayette
West Lafayette, United States
4 h-index
9 publications
199 citations
Oracle (United States)
Austin, United States
3 h-index
26 publications
394 citations
University of California San Diego
San Diego, United States
3 h-index
6 publications
117 citations
1–8 of 100
Venues
- IEEE Journal of Solid-State Circuits
9 publications · 425 citations
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- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
6 publications · 144 citations
6
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- IEEE Transactions on Computers
3 publications · 83 citations
3
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- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
3 publications · 265 citations
3
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- ACM Transactions on Architecture and Code Optimization
TACO · 2 publications · 25 citations
2
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