Debjit Sinha

Yield-Aware Cache Architectures

Serkan Özdemir, Debjit Sinha, Gokhan Memik et al. · Proceedings of the ... annual International Symposium on Microarchitecture/Proceedings of the annual International Symposium on Microarchitecture · 2006 · 112 citations

Hardware Security, Power-aware Computing, Memory Architecture +15

Statistical gate sizing for timing yield optimization

Debjit Sinha, Narendra Shenoy, Hai Zhou · ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005. · 2005 · 48 citations

Hardware Security, Statistical Gate Sizing, Physical Design (Electronics) +13

Advances in Computation of the Maximum of a Set of Gaussian Random Variables

Debjit Sinha, Hai Zhou, Narendra Shenoy · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2007 · 46 citations

Mathematical Programming, Engineering, Computational Complexity +18

Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment

Arindam Mallik, Debjit Sinha, Prithviraj Banerjee et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2007 · 39 citations

Engineering, Power Optimization (Eda), Electronic Design +19

TAU 2014 contest on removing common path pessimism during timing analysis

Jin Hu, Debjit Sinha, Igor Keller · 2014 · 30 citations

Undesired Pessimism, Engineering, Computational Complexity +16