Narendra Shenoy

Improved logic synthesis algorithms for table look up architectures

Rajeev Murgai, Narendra Shenoy, Robert K. Brayton et al. · 2002 · 208 citations

Engineering, Computer Architecture, System-level Design +19

Logic synthesis for programmable gate arrays

Rajeev Murgai, Yoshihito Nishizaki, Narendra Shenoy et al. · 1990 · 192 citations

Engineering, Computer Architecture, Formal Verification +16

Logic synthesis for programmable gate arrays

Rajeev Murgai, Y. Nishizaki, Narendra Shenoy et al. · 27th ACM/IEEE Design Automation Conference · 2002 · 130 citations

Engineering, Computer Architecture, Formal Verification +16

Efficient implementation of retiming

Narendra Shenoy, Richard Rudell · International Conference on Computer Aided Design · 1994 · 119 citations

Circuit Complexity, Engineering, Vlsi Design +16

Performance directed synthesis for table look up programmable gate arrays

Rajeev Murgai, Narendra Shenoy, Robert K. Brayton et al. · 2002 · 114 citations

Engineering, Vlsi Design, Delay Optimization +16