2002 · 209 citations · 12 references
EngineeringComputer EngineeringComputer ScienceAlgorithmsComputer ArchitectureField-programmable Gate ArraysCombinational Logic DescriptionDigital Logic DesignField-programmable Gate Array ArchitectureFpga ArchitectureLogic SynthesisLookup TablesCombinational Circuit OptimizationCombinational Logic SynthesisLogic OptimizationLookup Table ArchitecturesLookup Table DesignLut ArchitectureLut-based Logic Optimization
The authors address the problem of synthesis for a popular class of programmable gate array architecture-the table look-up architectures. These use lookup table memories to implement logic functions. The authors present improved techniques for minimizing the number of table look up blocks used to implement a combinational circuit. On average, the results obtained on a set of benchmarks are 15-29% better than results obtained by previous approaches.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Improved logic synthesis algorithms for table look up architectures
Rajeev Murgai, Narendra Shenoy, Robert K. Brayton et al. · 2002 · 209 citations
Logic synthesis for programmable gate arrays
Rajeev Murgai, Yoshihito Nishizaki, Narendra Shenoy et al. · 1990 · 194 citations