An Integrated Quad-Core Opteron Processor

Abstract

An integrated quad-core times86 processor is implemented in a 65nm 11M SOI CMOS process. Based on an enhanced Opterontrade core, the SoC-developed processor employs power- and thermal-management techniques throughout the design. The SRAM cache designs target process variation considerations and future process scalability. A DDR2/DDR3 combo-PHY and HT3 I/Os provide high-bandwidth interfaces.