Concepedia

Local Interconnect Optimization

Local Interconnect Optimization is a methodological framework in interconnect design that focuses on enhancing the performance, power efficiency, and area utilization of short-range wiring within a confined region of an integrated circuit by applying targeted routing, buffering, and sizing strategies distinct from global interconnect optimization techniques.

18

Publications

503

Citations

78

Authors

20

Institutions

Publications per year

2017–2026

1

Parents

Publications

18

FreePDK15

Kirti Bhanushali, W. Rhett Davis · 2015 · 83 citations

, , +15

Frame packing in real-time communication

Kristian Sandström, C. Norstom, M. Ahlmark · 2002 · 54 citations

, , +15

A scaling scheme for interconnect in deep-submicron processes

K. Rahmat, O.S. Nakagawa, Soo‐Young Oh et al. · 2002 · 53 citations

, , +17

Optimal Wiring of Movable Terminals

Gopal, Coppersmith, Wong · IEEE Transactions on Computers · 1983 · 52 citations

, , +17

Lithium-Intercalated Graphene Interconnects: Prospects for On-Chip Applications

Atul Kumar Nishad, Rohit Sharma · IEEE Journal of the Electron Devices Society · 2016 · 44 citations · Full text

, , +17

1–5 of 18

Authors

78

  1. AN
    Azad Naeemi

    Georgia Institute of Technology, United States

    3 publications · 55 citations

    3

    h-index

  2. CP
    Chenyun Pan

    Georgia Institute of Technology, United States

    2 publications · 45 citations

    2

    h-index

  3. MC
    Michael C. Smayling

    Tela Innovations (United States), United States

    2 publications · 30 citations

    2

    h-index

  4. CN
    C. Norstom

    Mälardalen University, Sweden

    1 publications · 54 citations

    1

    h-index

  5. JM
    J. M. Hill

    University of Florida, United States

    1 publications · 14 citations

    1

    h-index

1–5 of 78

Institutions

20

  1. Georgia Institute of Technology

    Atlanta, United States

    3 h-index

    10 publications

    168 citations

  2. Eindhoven University of Technology

    Eindhoven, The Netherlands

    2 h-index

    2 publications

    49 citations

  3. Hewlett-Packard (United States)

    Palo Alto, United States

    2 h-index

    6 publications

    240 citations

  4. Tela Innovations (United States)

    Los Gatos, United States

    2 h-index

    2 publications

    30 citations

  5. NEC (Japan)

    Tokyo, Japan

    1 h-index

    3 publications

    45 citations

  6. Vassar College

    Town of Poughkeepsie, United States

    1 h-index

    1 publications

    16 citations

  7. IBM Research - Thomas J. Watson Research Center

    Yorktown Heights, United States

    1 h-index

    3 publications

    156 citations

  8. Sequoia (United States)

    Mountain View, United States

    1 h-index

    1 publications

    16 citations

1–8 of 20

Venues

  1. 2

    h-index

  2. IEEE Journal of the Electron Devices Society

    1 publications · 44 citations

    1

    h-index

  3. IEEE Transactions on Computers

    1 publications · 52 citations

    1

    h-index

  4. Journal of Electronic Testing

    JETTA · 1 publications · 11 citations

    1

    h-index

  5. 1

    h-index

1–5