IEEE Transactions on Computers · 1983 · 52 citations · 8 references
EngineeringComputer EngineeringElectrical EngineeringDesign OptimizationOptimizationVlsi DesignCombinatorial OptimizationInterconnect DesignLayout OptimizationPhysical DesignRoutingVery-large-scale Integration LayoutHeuristicsInterconnect Layout OptimizationInterconnect OptimizationLocal Interconnect OptimizationObjective Function FormulationPlacement AlgorithmsPolynomial-time AlgorithmsWire Sizing
In this paper we consider the problem of local wiring in a VLSI chip. The problem is one of interconnecting two sets of terminals, one set on each side of a wiring channel, in accordance with a given interconnection pattern, and to accomplish this while minimizing some objective function. We make the further assumption that the terminals are not rigidly positioned and can be "moved" provided that this does not change the structural intent of the circuit. Several objective functions are considered-channel width, channel length, channel area, channel perimeter, number of via holes, as well as some constrained objective functions. For some of these objective functions, we are able to find polynomial time optimal algorithms while, for others, we prove NP-completeness and suggest efficient heuristics.
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