Concepedia

Gate Layout Design

Gate Layout Design is a methodological framework within ro-ro terminal design that specifies the spatial configuration and operational arrangement of vehicle entry and exit points to optimize traffic flow, security control, and processing efficiency at terminal gate systems.

63

Publications

5.2K

Citations

199

Authors

82

Institutions

Publications per year

2017–2026

6

Parents

Publications

63

Logic Circuits with Carbon Nanotube Transistors

Adrian Bachtold, P. Hadley, Takeshi Nakanishi et al. · Science · 2001 · 2.6K citations · Full text

, , +17

1.8 mΩ·cm<sup>2</sup>vertical GaN-based trench metal–oxide–semiconductor field-effect transistors on a free-standing GaN substrate for 1.2-kV-class operation

Tohru OKA, Tsutomu Ina, Yukihisa Ueno et al. · Applied Physics Express · 2015 · 350 citations

, , +15

A dense gate matrix layout method for MOS VLSI

A.D. Lopez, H.-F.S. Law · IEEE Transactions on Electron Devices · 1980 · 141 citations

, , +17

A novel Si tunnel FET with 36mV/dec subthreshold slope based on junction depleted-modulation through striped gate configuration

Qianqian Huang, Ru Huang, Zhan Zhan et al. · 2012 · 128 citations

, , +11

PROUD: a sea-of-gates placement algorithm

Ren‐Song Tsay, E.S. Kuh, Chi‐Ping Hsu · IEEE Design & Test of Computers · 1988 · 127 citations

, , +15

1–5 of 63

Authors

199

  1. HL
    H.-F.S. Law

    Nokia (United States), United States

    4 publications · 242 citations

    4

    h-index

  2. AL
    A.D. Lopez

    Nokia (United States), United States

    3 publications · 225 citations

    3

    h-index

  3. JF
    J.G. Fossum

    University of Florida, United States

    2 publications · 138 citations

    2

    h-index

  4. LC
    Li Chen

    University of Saskatchewan, Canada

    2 publications · 53 citations

    2

    h-index

  5. JS
    Jean‐Luc Schanen

    Laboratoire de Génie Électrique de Grenoble, France

    2 publications · 60 citations

    2

    h-index

1–5 of 199

Institutions

82

  1. University of South Carolina

    Columbia, United States

    3 h-index

    4 publications

    72 citations

  2. Nokia (United States)

    Coppell, United States

    3 h-index

    3 publications

    181 citations

  3. TRIUMF

    Vancouver, Canada

    2 h-index

    2 publications

    53 citations

  4. Institute of Microelectronics

    Beijing, China

    2 h-index

    8 publications

    915 citations

  5. Instituto Nacional de Pesquisas Espaciais

    São José dos Campos, Brazil

    2 h-index

    3 publications

    86 citations

  6. University of Florida

    Gainesville, United States

    2 h-index

    4 publications

    276 citations

  7. University of Illinois Urbana-Champaign

    Urbana, United States

    2 h-index

    4 publications

    181 citations

  8. University of California, Berkeley

    Berkeley, United States

    2 h-index

    4 publications

    394 citations

1–8 of 82

Venues

  1. 9

    h-index

  2. IEEE Transactions on Electron Devices

    4 publications · 303 citations

    4

    h-index

  3. IEEE Electron Device Letters

    2 publications · 76 citations

    2

    h-index

  4. 1

    h-index

  5. Journal of Materials Processing Technology

    1 publications · 38 citations

    1

    h-index

1–5