A dense gate matrix layout method for MOS VLSI

TLDR

The authors present a rapid, systematic method for VLSI chip layout. The method uses a matrix of intersecting rows and columns to place transistors and interconnects, enabling automatic updates to new design rules. The resulting layouts achieve high device density, simplify error checking, and have been applied to a 20,000‑transistor VLSI section.

Abstract

A rapid and systematic method for performing chip layout of VLSI circuits is described. This method utilizes the configuration of a matrix composed of intersecting rows and columns to provide transistor placement and interconnections. This structure, which is orderly and regular, gives high device-packing density and allows ease of checking for layout errors. Resulting layouts may be updated to new design rules automatically. This method has been used in the layout of a 20 000-transistor section of a VLSI circuit.