Design Rule Checking
Design Rule Checking is a verification methodology in integrated circuit design that systematically ensures a physical layout adheres to a foundry’s prescribed geometric and connectivity constraints to guarantee manufacturability and electrical correctness.
208
Publications
7.3K
Citations
656
Authors
175
Institutions
Publications per year
2017–2026
26
Variants
Drc
Parents
208
Automatic rule-based checking of building designs
Charles M. Eastman, Jae-min Lee, Yeon-suk Jeong et al. · Automation in Construction · 2009 · 686 citations
Firewall design: consistency, completeness, and compactness
Mohamed G. Gouda, Xiaotong Liu · 2004 · 198 citations
1–5 of 208
656
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1–5 of 656
175
University of California, Berkeley
Berkeley, United States
9 h-index
25 publications
2.4K citations
IBM (United States)
Armonk, United States
9 h-index
20 publications
291 citations
Carnegie Mellon University
Pittsburgh, United States
8 h-index
25 publications
852 citations
University of California San Diego
San Diego, United States
8 h-index
22 publications
653 citations
Cadence Design Systems (United States)
San Jose, United States
7 h-index
17 publications
253 citations
Toshiba (Japan)
Tokyo, Japan
7 h-index
26 publications
400 citations
Intel (United States)
Santa Clara, United States
6 h-index
7 publications
148 citations
Advanced Micro Devices (United States)
Sunnyvale, United States
5 h-index
15 publications
327 citations
1–8 of 175
20 publications · 451 citations
14
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15 publications · 396 citations
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Conference · 15 publications · 492 citations
12
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Conference · 5 publications · 94 citations
5
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Conference · 4 publications · 209 citations
4
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