Design For Testability Checking

"Design for Test在玩家中 Checking" is a formal verification process within electronic design automation that ensures a circuit design adheres to specific testability rules and structures—such as scan chains, built-in self-test mechanisms, and fault observability—enabling efficient detection and diagnosis of manufacturing defects, thereby distinguishing it from general design rule checking by focusing exclusively on testability enhancements.

57

Publications

2.5K

Citations

131

Authors

56

Institutions

Publications per year

2017–2026

3

Authors

131

  1. FA
    Frederik Arbeiter

    Karlsruhe Institute of Technology, Germany

    3 publications · 44 citations

    3

    h-index

  2. WM
    W. Maly

    Carnegie Mellon University, United States

    2 publications · 142 citations

    2

    h-index

  3. AG
    Anne Gattiker

    IBM Research - Austin, United States

    2 publications · 142 citations

    2

    h-index

  4. JJ
    Jawahar Jain

    Fujitsu (United States), United States

    2 publications · 96 citations

    2

    h-index

  5. ML
    Moshe Levinger

    IBM Research - Haifa, Israel

    2 publications · 213 citations

    2

    h-index

1–5 of 131

Venues

  1. Design Automation Conference

    Conference · 4 publications · 92 citations

    4

    h-index

  2. IEEE Design & Test of Computers

    4 publications · 162 citations

    4

    h-index

  3. Fusion Engineering and Design

    3 publications · 44 citations

    3

    h-index

  4. IEEE Transactions on Computers

    3 publications · 445 citations

    3

    h-index

  5. 3

    h-index

1–5