Design For Testability Checking
"Design for Test在玩家中 Checking" is a formal verification process within electronic design automation that ensures a circuit design adheres to specific testability rules and structures—such as scan chains, built-in self-test mechanisms, and fault observability—enabling efficient detection and diagnosis of manufacturing defects, thereby distinguishing it from general design rule checking by focusing exclusively on testability enhancements.
57
Publications
2.5K
Citations
131
Authors
56
Institutions
Publications per year
2017–2026
3
Parents
57
Test program generation for functional verification of PowerPC processors in IBM
Aharon Aharon, Dave Goodman, Moshe Levinger et al. · 1995 · 165 citations
Current signatures: application
Anne Gattiker, W. Maly · 2002 · 117 citations
Engineering, Computer Engineering, Electrical Engineering +15
1–5 of 57
131
3
h-index
2
h-index
2
h-index
2
h-index
2
h-index
1–5 of 131
56
Karlsruhe Institute of Technology
Karlsruhe, Germany
3 h-index
10 publications
140 citations
Mentor Technologies
Tulsa, United States
2 h-index
4 publications
286 citations
KU Leuven
Leuven, Belgium
2 h-index
7 publications
100 citations
Carnegie Mellon University
Pittsburgh, United States
2 h-index
6 publications
334 citations
National Tsing Hua University
Hsinchu, Taiwan
2 h-index
5 publications
180 citations

Université de Montpellier
Montpellier, France
2 h-index
8 publications
348 citations
IBM Research - Haifa
Haifa, Israel
2 h-index
9 publications
1.4K citations
IBM (United States)
Armonk, United States
2 h-index
2 publications
49 citations
1–8 of 56
Conference · 4 publications · 92 citations
4
h-index
4 publications · 162 citations
4
h-index
3 publications · 44 citations
3
h-index
3 publications · 445 citations
3
h-index
3 publications · 156 citations
3
h-index
1–5