Geometric Rule Checking

Geometric Rule Checking is a formal verification method in integrated circuit design that systematically enforces manufacturing constraints by evaluating layout geometries against a set of minimum spacing, width, and overlap rules to ensure fabricability and reliability.

22

Publications

555

Citations

48

Authors

22

Institutions

Publications per year

2017–2026

0

Authors

48

  1. LS
    Larry Seiler

    Intel (United States), United States

    2 publications · 42 citations

    2

    h-index

  2. MH
    Michael H. Arnold

    University of California, Berkeley, United States

    2 publications · 45 citations

    2

    h-index

  3. RK
    Rajiv Kane

    University of Minnesota, United States

    2 publications · 24 citations

    2

    h-index

  4. SS
    Sartaj Sahni

    University of Florida, United States

    2 publications · 24 citations

    2

    h-index

  5. JK
    John K. Ousterhout

    University of California, Berkeley, United States

    2 publications · 45 citations

    2

    h-index

1–5 of 48

Venues

  1. Design Automation Conference

    Conference · 5 publications · 107 citations

    5

    h-index

  2. 3

    h-index

  3. Computers & Graphics

    2 publications · 125 citations

    2

    h-index

  4. 19th Design Automation Conference

    Conference · 2 publications · 27 citations

    2

    h-index

  5. 21st Design Automation Conference Proceedings

    Conference · 1 publications · 12 citations

    1

    h-index

1–5