Electrical Rule Checking is a verification methodology within electronic design automation that systematically ensures a circuit design adheres to predefined electrical constraints and connectivity rules, distinguishing it from geometric or layout-based design rule checking by focusing on functional and electrical integrity.
13
Publications
256
Citations
45
Authors
21
Institutions
Publications per year
2017–2026
0
Variants
Erc
Parents
Publications
13
Detection of an antenna effect in VLSI designs
W. Maly, C. Ou-Yang, Saswati Ghosh et al. · 2002 · 32 citations
Engineering, Computer Engineering, Electrical Engineering +16
1–5 of 13
Authors
45
- RP
2
h-index
- MZ
2
h-index
- SY
2
h-index
- PG
2
h-index
- JH
2
h-index
1–5 of 45
Institutions
21
IBM (United States)
Armonk, United States
3 h-index
9 publications
125 citations
General Electric (United States)
Boston, United States
2 h-index
2 publications
24 citations
United States Department of Defense
Washington, United States
2 h-index
3 publications
68 citations
Oracle (United States)
Austin, United States
2 h-index
4 publications
106 citations
Shanghai University
Shanghai, China
2 h-index
6 publications
159 citations
University of California, Santa Cruz
Santa Cruz, United States
1 h-index
1 publications
10 citations
Intel (United States)
Santa Clara, United States
1 h-index
1 publications
20 citations
University of Hong Kong
Pok Fu Lam, Hong Kong
1 h-index
1 publications
20 citations
1–8 of 21
Venues
- Design Automation Conference
Conference · 2 publications · 38 citations
2
h-index
- ACM Journal on Emerging Technologies in Computing Systems
JETC · 1 publications · 33 citations
1
h-index
- IEEE Journal of Solid-State Circuits
1 publications · 16 citations
1
h-index
- IEEE Transactions on Applied Superconductivity
1 publications · 26 citations
1
h-index
- 20th Design Automation Conference Proceedings
Conference · 1 publications · 12 citations
1
h-index
1–5