Electrically alterable avalanche-injection-type MOS READ-ONLY memory with stacked-gate structure

H. Iizuka, F. Masuoka, Tai Satô, +1

IEEE Transactions on Electron Devices

Non-volatile MemoryElectrical EngineeringEngineeringNanoelectronicsStacked-gate Structure +13

An optimally designed process for submicron MOSFETs

T. Shibata, K. Hieda, M. Sato, +3

Electrical EngineeringEngineeringVlsi DesignCircuit DesignSaturation Drain Characteristics +8

A new bird's-beak free field isolation technology for VLSI devices

K. Kurosawa, T. Shibata, H. Iizuka

EngineeringVlsi DesignNew TechnologyDevice IntegrationInterconnect (Integrated Circuits) +18

An optimally designed process for submicrometer MOSFET's

T. Shibata, K. Hieda, Masaki Sato, +3

IEEE Transactions on Electron Devices

Low-power ElectronicsElectrical EngineeringEngineeringCircuit SystemMicrofabrication +11

A simplified box (buried-oxide) isolation technology for megabit dynamic memories

T. Shibata, Ryo Nakayama, K. Kurosawa, +3

Non-volatile MemoryEngineeringBox StructureComputer ArchitectureMegabit Dynamic Memories +14

Growth of single crystalline γ-Al2O3 layers on silicon by metalorganic molecular beam epitaxy

H. Iizuka, K. Yokoo, Shoichi Ono

Applied Physics Letters

Oxide HeterostructuresMaterials ScienceMaterials EngineeringAluminium NitrideEngineering +11

Limiting factors for programming EPROM of reduced dimensions

M. Wada, S. Mimura, H. Nihira, +1

Mathematical ProgrammingNon-volatile MemoryComputational Complexity TheoryEngineeringVlsi Design +17

Characterization of two step impact ionization and its influence in NMOS and PMOS VLSI's

J. Matsunaga, H.S. Momose, H. Iizuka, +1

Secondary ImpactEngineeringIon ProcessSemiconductor DeviceIon Implantation +14

A new write/erase method to improve the read disturb characteristics based on the decay phenomena of stress leakage current for flash memories

Tetsuo Endoh, Kazuhiro Shimizu, H. Iizuka, +1

IEEE Transactions on Electron Devices

Flash MemoriesNon-volatile MemoryElectrical EngineeringEngineeringTunnel Oxide +9

Optimum design of dual-control gate cell for high-density EEPROM's

K. Hieda, M. Wada, T. Shibata, +3

IEEE Transactions on Electron Devices

Electrical EngineeringEngineeringVlsi DesignNanoelectronicsElectronic Engineering +13