An optimally designed process for submicron MOSFETs

Abstract

An n-channel MOS process has been optimized to yield desirable characteristics for submicron channel length MOSFETs. Process/device simulation is extensively used to find an optimized processing sequence compatible to typical production line processes. The simulation results show an excellent agreement to experimental data. We have obtained long-channel subthreshold characteristics, saturation drain characteristics up to 5V, and minimized substrate bias effects for transistors with channel lengths as small as 0.5µ. The short channel effects have been also minimized. A unique self-aligned silicidation technology which has been developed to reduce the increased resistance of down-scaled junctions is also presented.