Kuo-Pin Chang

Study of fast initial charge loss and it's impact on the programmed states Vt distribution of charge-trapping NAND Flash

Chih‐Ping Chen, Hang-Ting Lue, Chih-Chang Hsieh et al. · 2010 · 50 citations

Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D <sc>NAND</sc> Flash Memory Devices

Yi‐Hsuan Hsiao, Hang-Ting Lue, Wei-Chen Chen et al. · IEEE Transactions on Electron Devices · 2014 · 44 citations

Non-volatile Memory, Engineering, Vlsi Design +16

A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts

Shih‐Hung Chen, Hang-Ting Lue, Yen-Hao Shih et al. · 2012 · 39 citations

Engineering, Vlsi Design, Computer Architecture +16

A highly scalable vertical gate (VG) 3D NAND Flash with robust program disturb immunity using a novel PN diode decoding structure

Chun-Hsiung Hung, Hang-Ting Lue, Kuo-Pin Chang et al. · 2011 · 26 citations

Scalable Vertical Gate, Non-volatile Memory, Electrical Engineering +10

A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)

Chih‐Ping Chen, Hang-Ting Lue, Kuo-Pin Chang et al. · 2012 · 25 citations

3D Ic Architecture, Electrical Engineering, Engineering +14