Study of fast initial charge loss and it's impact on the programmed states Vt distribution of charge-trapping NAND Flash

Abstract

We report for the first time a fast initial charge loss (within 1 sec) in charge-trapping (CT) NAND devices. Using a fast-response pulse I–V system retention transients from μsec to sec are characterized and the correlation with programmed states Vt distribution in various NAND Flash test chips is examined. We clarify that the impacts of fast initial charge loss are: (1) it produces a programmed state Vt offset in the various program-verify (PV) levels, and (2) it broadens the Vt distribution thus threatens the MLC capability. Our findings suggest that both high-K/metal-gate and barrier engineered tunneling barrier approaches should be optimized in order to minimize the initial charge loss. We also propose a “refill” method to suppress this effect, and have successfully demonstrated tight Vt distributions in a BE-SONOS CT NAND test chip.