Mold deformation in nanoimprint lithography

F. Lazzarino, C. Gourgon, Patrick Schiavone, +1

Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena

Large AreaEngineeringMechanical EngineeringSoft MatterMolding (Process) +16

Influence of pattern density in nanoimprint lithography

C. Gourgon, C. Perret, Guillaume Micouin, +4

Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena

Materials ScienceEngineeringBeam LithographyFlexible ElectronicsMicrofabrication +12

Inflection points in interconnect research and trends for 2nm and beyond in order to solve the RC bottleneck

Zs. Tôkei, V. Vega, Gayle Murdoch, +34

EngineeringVlsi DesignInterconnection Network ArchitectureInflection PointsInterconnect (Integrated Circuits) +22

Freeform illumination sources: an experimental study of source-mask optimization for 22-nm SRAM cells

Joost Bekaert, Bart Laenens, Staf Verhaegen, +22

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

EngineeringVlsi DesignElectron-beam LithographyOptic Design22-Nm Sram Cells +19

Influence of residual solvent in polymers patterned by nanoimprint lithography

C. Gourgon, J.H. Tortai, F. Lazzarino, +4

Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena

EngineeringMechanical EngineeringResidual SolventPolymersChemical Engineering +15

Replication of sub-40nm gap nanoelectrodes over an 8-in. substrate by nanoimprint lithography

J. Tallal, D. Peyrade, F. Lazzarino, +5

Microelectronic Engineering

Materials ScienceEngineeringNanoimprint LithographyBeam LithographyMicrofabrication +11

Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond

Anshul Gupta, Olalla Varela Pedreira, Zheng Tao, +32

Materials ScienceElectrical EngineeringMetal AssessmentEngineeringMicrofabrication +10

A novel CBRAM integration using subtractive dry-etching process of Cu enabling high-performance memory scaling down to 10nm node

A. Redolfi, L. Goux, N. Jossart, +7

Simulation and measurement of the capacitance benefit of air gap interconnects for advanced technology nodes

Vishnuvarthan Kumaresan, Christopher Wilson, Patrick Verdonck, +6

Microelectronic Engineering

Electrical EngineeringPhysical Design (Electronics)EngineeringAdvanced Packaging (Semiconductors)Nanoelectronics +12