T.L. Lee

Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application

Chien‐Hao Chen, T.L. Lee, Tuo‐Hung Hou et al. · 2004 · 115 citations

Engineering, Silicon On Insulator, Stress Modulation Effect +16

A 3nm CMOS FinFlex™ Platform Technology with Enhanced Power Efficiency and Performance for Mobile SoC and High Performance Computing Applications

Shien-Yang Wu, M.C. Chiang, C.Y. Lin et al. · 2022 International Electron Devices Meeting (IEDM) · 2022 · 49 citations

Low-power Electronics, Electrical Engineering, Cmos Platform Technology +15

A 90-nm CMOS device technology with high-speed, general-purpose, and low-leakage transistors for system on chip applications

Chung-Cheng Wu, Yuet‐Kin Leung, C. S. Chang et al. · 2003 · 46 citations

Engineering, Vlsi Design, Power Electronics +17

65nm CMOS high speed, general purpose and low power transistor technology for high volume foundry application

S.K.H. Fung, H.T. Huang, Sheng-Jen Cheng et al. · 2004 · 45 citations · Full text

Low-power Electronics, Electrical Engineering, Engineering +15

A highly manufacturable 28nm CMOS low power platform technology with fully functional 64Mb SRAM using dual/tripe gate oxide process

Shien-Yang Wu, J.J. Liaw, Chih‐Yung Lin et al. · Symposium on VLSI Technology · 2006 · 42 citations

Low-power Electronics, Mb Sram Test-chip, Electrical Engineering +13