K. Fukasaku

High performance CMOSFET technology for 45nm generation and scalability of stress-induced mobility enhancement technique

A. Oishi, Osamu Fujii, T. Yokoyama et al. · 2005 · 42 citations

Low-power Electronics, Electrical Engineering, Technology Cmosfet +14

A 45nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL

H. Nii, T. Sanuki, Y. Okayama et al. · 2006 · 22 citations

Engineering, Ultra High Na, Wafer Scale Processing +16

A 100 nm node CMOS technology for practical SOC application requirement

A. Ono, K. Fukasaku, Tadayoshi Hirai et al. · 2002 · 20 citations

Low-power Electronics, System On Chip, Electrical Engineering +14

A 70 nm gate length CMOS technology with 1.0 V operation

A. Ono, K. Fukasaku, Tomoko Matsuda et al. · 2002 · 16 citations

Low-power Electronics, Gate Dielectrics, Electrical Engineering +11

Management of Power and Performance with Stress Memorization Technique for 45nm CMOS

A. Eiho, T. Sanuki, E. Morifuji et al. · 2007 · 10 citations

Low-power Electronics, Electrical Engineering, Appropriate Stressor +12