H.J. Tao

Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application

Chien‐Hao Chen, T.L. Lee, Tuo‐Hung Hou et al. · 2004 · 115 citations

Engineering, Electrical Engineering, Materials Science +14

High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme

Chau-Neng Wu, Dongyang Lin, A. Keshavarzi et al. · 2010 · 106 citations

Engineering, Electrical Engineering, Microelectronics +16

A 0.13 μm CMOS technology with 193 nm lithography and Cu/low-k for high performance applications

K.K. Young, S.Y. Wu, Chung-Cheng Wu et al. · 2002 · 50 citations

Engineering, Computer Engineering, Electrical Engineering +15

A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 μm<sup>2</sup> SRAM cell

Kuan‐Lun Cheng, Chung-Cheng Wu, Y.P. Wang et al. · 2007 · 37 citations

Engineering, Computer Engineering, Electrical Engineering +16

Two-frequency C-V correction using five-element circuit model for high-k gate dielectric and ultrathin oxide

Wei-Ting Wu, Bing‐Yue Tsui, Y.P. Huang et al. · IEEE Electron Device Letters · 2006 · 29 citations

Engineering, Electrical Engineering, Materials Science +17