A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 μm<sup>2</sup> SRAM cell

Abstract

A highly scaled, high performance 45 nm CMOS technology utilizing extensive immersion lithography to achieve the industry's highest scaling factor with ELK (k=2.55) BEOL is presented. A record gate density 2.4X higher than that of 65 nm is achieved. Refined strained-CMOS demonstrated 1200/750 μA/μm Idsat at 100 nA/μm Ioff, Vdd=1 V, which has the best Ion-Lg performance reported for bulk CMOS device. The proposed 45 nm technology is not only manufacturing friendly but also has well-controlled leakage and mismatch evidenced by a functional 32 Mb 0.242 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SRAM.