M. Woo

Low cost 65nm CMOS platform for Low Power & General Purpose applications

F. Arnaud, B. Duriez, B. Tavel et al. · 2004 · 24 citations

Engineering, Computer Engineering, Electrical Engineering +15

Implementation of diode and bipolar triggered SCRs for CDM robust ESD protection in 90nm CMOS ASICs

Ciaran J. Brennan, Shunhua Chang, M. Woo et al. · Microelectronics Reliability · 2007 · 23 citations

Engineering, Electrical Engineering, Microelectronics +5

ESD-induced oxide breakdown on self-protecting GG-nMOSFET in 0.1-μm CMOS technology

Akram Salman, Robert Gauthier, C. Putnam et al. · IEEE Transactions on Device and Materials Reliability · 2003 · 21 citations

Engineering, Electrical Engineering, Electronic Materials +16

Study of factors limiting ESD diode performance in 90nm CMOS technologies and beyond

Kiran Chatty, Robert Gauthier, C. Putnam et al. · 2005 · 20 citations

Engineering, Electrical Engineering, Electronic Materials +16

Thin oxynitride solution for digital and mixed-signal 65nm CMOS platform

B. Tavel, M. Bidaud, N. Emonet et al. · 2004 · 18 citations

Engineering, Electrical Engineering, Physics +17