T. Kanemura

Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length

K. Okano, T. Izumida, H. Kawasaki et al. · 2006 · 76 citations

Engineering, Electrical Engineering, Microfabrication +16

High-Performance FinFET with Dopant-Segregated Schottky Source/Drain

A. Kaneko, A. Yagishita, K. Yahashi et al. · 2006 · 53 citations

Engineering, Electrical Engineering, Electronic Materials +11

Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm Node and Beyond

Hikaru Kawasaki, K. Okano, A. Kaneko et al. · 2006 · 44 citations

Engineering, Computer Engineering, Electrical Engineering +16

Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension

A. Kaneko, A. Yagishita, K. Yahashi et al. · 2006 · 44 citations

Engineering, Electrical Engineering, Low-power Design +11

FinFET: the prospective multi-gate device for future SoC applications

S. Inaba, K. Okano, T. Izumida et al. · Proceedings of ESSCIRC · 2006 · 10 citations

Engineering, Computer Engineering, Electrical Engineering +13