Edward J. Nowak

Challenges and Limitations of CMOS Scaling for FinFET and Beyond Architectures

Ali Razavieh, P. Zeitzoff, Edward J. Nowak · IEEE Transactions on Nanotechnology · 2019 · 260 citations

Cmos Scaling, Engineering, Vlsi Design +18

A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology

Rajiv Joshi, Keunwoo Kim, R. Williams et al. · 2007 · 29 citations

Electrical Engineering, Engineering, Vlsi Design +11

Crystallographic-Orientation-Dependent Gate-Induced Drain Leakage in Nanoscale MOSFETs

R. K. Pandey, K. V. R. M. Murali, S. Furkay et al. · IEEE Transactions on Electron Devices · 2010 · 29 citations

Device Modeling, Electrical Engineering, Engineering +14

Self-Consistent and Efficient Electro-Thermal Analysis for Poly/Metal Gate FinFETs

Satish Kumar, Rajiv Joshi, Ching-Te Chuang et al. · 2006 · 21 citations

Device Modeling, Thin Si Layer, Electrical Engineering +14

Channel electron mobility dependence on lateral electric field in field-effect transistors

D. Hoyniak, Edward J. Nowak, R. L. Anderson · Journal of Applied Physics · 2000 · 19 citations

Device Modeling, Semiconductor Technology, Electrical Engineering +14