Jiefeng Lin

RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications

C.-H. Jan, M. Agostinelli, H. Deshpande et al. · 2010 · 84 citations

Engineering, Vlsi Design, Rf Soc +16

A 32nm SoC platform technology with 2<sup>nd</sup> generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications

C.-H. Jan, M. Agostinelli, Markus J. Buehler et al. · 2009 · 75 citations

Engineering, Vlsi Design, Computer Architecture +20

A 1.1 GHz 12 $\mu$A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen et al. · IEEE Journal of Solid-State Circuits · 2008 · 71 citations

Non-volatile Memory, Engineering, Vlsi Design +20

A 65nm CMOS SOC Technology Featuring Strained Silicon Transistors for RF Applications

I. Post, M.S. Akbar, G. Curello et al. · 2006 · 57 citations

Low-power Electronics, Pmos Transistors, Electrical Engineering +11

A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors

C.-H. Jan, Peng Bai, S. Biswas et al. · 2008 · 45 citations

Robust Reliability, Engineering, Vlsi Design +17