Hong Jo Ahn

6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET

Jay Im, Kevin Zheng, Adam Chou et al. · 2020 · 83 citations

Engineering, Vlsi Design, Clock Recovery +8

A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology

Fatih Hamzaoglu, Hong Jo Ahn, Uddalak Bhattacharya et al. · IEEE Journal of Solid-State Circuits · 2009 · 82 citations

Low-power Electronics, Electrical Engineering, Engineering +15

A 1.1 GHz 12 $\mu$A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen et al. · IEEE Journal of Solid-State Circuits · 2008 · 71 citations

Non-volatile Memory, Engineering, Vlsi Design +20

A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-¿ Metal-Gate CMOS Technology

Fatih Hamzaoglu, Hong Jo Ahn, Uddalak Bhattacharya et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 2008 · 37 citations

Low-power Electronics, Electrical Engineering, Engineering +13

A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications

Yuxiao Wang, Jiefeng Lin, Yat Hon Ng et al. · 2007 · 31 citations

Engineering, Vlsi Design, Emerging Memory Technology +20