Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 2008 · 37 citations · 14 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsVlsi DesignCmos Circuit DesignDynamic Power ReductionIntegrated Circuit DesignLeakage Power ReductionLow-power Cache DesignPower OptimizationActive Feedback ControlCache DesignCache Dynamic Power ReductionCache Leakage ReductionDynamic StabilityLeakage Current ReductionModular ArchitectureStability Enhancement
We report a 153Mb SRAM design that is optimized for a 45nm high-K metal-gate technology (Mistry et al., 2007). The design contains fully integrated dynamic forward-body-bias to achieve lower voltage operation while keeping low the area and power overhead. The dynamic sleep design, which was developed at the 65nm node (Zhang et al., 2005), is further enhanced with op-amp-based active-feedback control and on-die programmable reference-voltage generator. The new sleep design reduces the effect of PVT variation, leading to further power reduction. The modular architecture of the design also enables the 16KB-subarray to be used directly as the building block for a 6MB L2 cache in the Core <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TM</sup> 2 CPU (George, 2007). The design operates over 3.5GHz at 1.1V.
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