Leonard C. Pipes

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

K. Mistry, R. Chau, Changhwan Choi et al. · 2007 · 825 citations

Nm Logic Technology, Engineering, Vlsi Design +18

A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

C. Auth, C. Allen, A. Blattner et al. · 2012 · 749 citations

Low-power Cmos Technology, Engineering, Vlsi Design +19

A 14nm logic technology featuring 2<sup>nd</sup>-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm<sup>2</sup> SRAM cell size

S. Natarajan, M. Agostinelli, Sheikh A. Akbar et al. · 2014 · 521 citations

-Generation Finfet, Rectangular Fins, Engineering +16

A 10nm high performance and low-power CMOS technology featuring 3^rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects

C. Auth, A. Aliyarukunju, M. Asoro et al. · 2017 · 353 citations

Engineering, Integrated Circuits, High Performance +18

High performance 32nm logic technology featuring 2<sup>nd</sup> generation high-k + metal gate transistors

P. Packan, Sheikh A. Akbar, M Armstrong et al. · 2009 · 184 citations

Nm Logic Technology, Electrical Engineering, Engineering +13