T. Spooner

Mechanism of Co Liner as Enhancement Layer for Cu Interconnect Gap-Fill

Meng‐Dong He, Xingxing Zhang, T. Nogami et al. · Journal of The Electrochemical Society · 2013 · 109 citations

Natural Sciences, Materials Engineering, Materials Science +13

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

Kwangyou Seo, Bala Haran, Divya Gupta et al. · 2014 · 99 citations

Engineering, Computer Engineering, Electrical Engineering +17

Future on-chip interconnect metallization and electromigration

Chunhua Hu, James J. Kelly, Huai Huang et al. · 2018 · 70 citations

Engineering, Electrical Engineering, Materials Science +17

High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL

W.-H. Lee, Anya M. Waite, H. Nii et al. · 2006 · 55 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 0.13 μm CMOS platform with Cu/low-k interconnects for system on chip applications

T. Schiml, S. Biesemans, G. Brase et al. · 2002 · 53 citations

Engineering, Computer Engineering, Electrical Engineering +17