V. Mazzocchi - Concepedia

Author

V. Mazzocchi

Laboratoire d'Électronique des Technologies de l'Information

Also Known As

Mazzocchi, Vincent, V. Mazzocchi, Vincent Mazzocchi

Publications

872

Citations

H-Index

Concepts

All Affiliations

Laboratoire d'Électronique des Technologies de l'Information Commissariat à l'Énergie Atomique et aux Énergies Alternatives CEA Grenoble Université Grenoble Alpes Institut polytechnique de Grenoble

About

V. Mazzocchi is an author at Laboratoire d'Électronique des Technologies de l'Information specializing in engineering, applied physics, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	14	20	710
2	Applied Physics	14	18	632
3	Natural Sciences	3	3	97
4	Chemical Engineering	1	1	17
5	Chemistry	1	1	17

V. Mazzocchi

Publications

794

Citations

H-Index

Page 1

	Year	Citations
GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current Louis Hutin, C. Le Royer, J.-F. Damlencourt, IEEE Electron Device Letters EngineeringIntegrated CircuitsGeoi Pmosfets30-Nm Gate LengthSemiconductor Device	2010	122
Advances in 3D CMOS sequential integration P. Batude, M. Vinet, A. Pouydebasque, EngineeringVlsi DesignSequential Cmos IntegrationSilicon On InsulatorCmos Sequential Integration	2009	114
Detection of Single W-Centers in Silicon Yoann Baron, Alrik Durand, Péter Udvarhelyi, ACS Photonics	2022	74
3D monolithic integration: Technological challenges and electrical results M. Vinet, P. Batude, C. Tabone, Microelectronic Engineering 3D Ic ArchitectureEngineeringAdvanced Packaging (Semiconductors)Device IntegrationTechnological Challenges	2010	65
Breakthroughs in 3D Sequential technology Laurent Brunet, C. Fenouillet-Béranger, P. Batude, EngineeringComputer Architecture3D ModelingComputer-aided DesignIntegrated Circuits	2018	51
99.992% 28Si CVD-grown epilayer on 300 mm substrates for large scale integration of silicon spin qubits V. Mazzocchi, Benoît Bertrand, Louis Hutin, Journal of Crystal Growth Electrical EngineeringWafer Scale ProcessingEngineeringAdvanced Packaging (Semiconductors)Physics	2018	50
High performance 70nm gate length germanium-on-insulator pMOSFET with high-k/metal gate K. Romanjek, Louis Hutin, C. Le Royer, Solid-State Electronics Electrical EngineeringEngineeringNanoelectronicsElectronic EngineeringBias Temperature Instability	2009	40
3D monolithic integration P. Batude, M. Vinet, A. Pouydebasque, EngineeringDevice IntegrationComputer ArchitectureComputer-aided DesignIntegrated Circuits	2011	32
20nm gate length trigate pFETs on strained SGOI for high performance CMOS Louis Hutin, M. Cassé, C. Le Royer, SemiconductorsSemiconductor TechnologyElectrical EngineeringSub XmlnsEngineering	2010	30
Towards scalable silicon quantum computing M. Vinet, Louis Hutin, Benoît Bertrand, Quantum ScienceElectrical EngineeringSpintronicsEngineeringQuantum Computing	2018	29

Page 1