Full copper wiring in a sub-0.25 μm CMOS ULSI technology

D. Edelstein, J. Heidenreich, R. Goldblatt, +14

3D Ic ArchitectureElectrical EngineeringCu WiringFull Copper WiringEngineering +6

A 480-MHz RISC microprocessor in a 0.12-μm L/sub eff/ CMOS technology with copper interconnects

C. Akrout, Jörg Bialas, M. Canada, +14

IEEE Journal of Solid-State Circuits

EngineeringVlsi DesignComputer ArchitectureIntegrated CircuitsProcessor Architecture +14

A new planarization technique, using a combination of RIE and chemical mechanical polish (CMP)

B. Davarik, Charles W. Koburger, R. Schulz, +8

EngineeringEmerging Memory TechnologyMechanical EngineeringIntegrated CircuitsChemical Engineering +20

CMOS-on-SOI ESD protection networks

Steven H. Voldman, R. Schulz, J. K. Howard, +10

Hardware SecurityLow-power ElectronicsElectrical EngineeringEngineeringVlsi Design +9

UTBB FDSOI scaling enablers for the 10nm node

L. Grenouillet, Qinrang Liu, R. Wacquez, +31

EngineeringVlsi DesignComputer ArchitectureElectromagnetic CompatibilityUtbb Fdsoi Technology +17

History dependence of non-fully depleted (NFD) digital SOI circuits

F. Assaderaghi, G. Shahidi, M. Hargrove, +11

Non-volatile MemoryElectrical EngineeringEngineeringVlsi DesignHistory Dependence +11

A high-performance sub-0.25 μm CMOS technology with multiple thresholds and copper interconnects

L.T. Su, R. Schulz, J. Adkisson, +26

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignAdvanced Packaging (Semiconductors) +13

A high-performance 0.08 μm CMOS

L.T. Su, S. Subbanna, E.F. Crabbé, +14

Low-power ElectronicsElectrical EngineeringμM CmosEngineeringVlsi Design +9

CMOS-on-SOI ESD protection networks

Steven H. Voldman, R. Schulz, J. K. Howard, +10

Journal of Electrostatics

Hardware SecurityEngineeringVlsi DesignComputer EngineeringTrusted Execution Environment +1

High performance 0.18 μm SOI CMOS technology

E. Leobandung, E. Barth, M. Sherony, +16

Low-power ElectronicsElectrical EngineeringHigh Performance 0.18EngineeringVlsi Design +10