A 480-MHz RISC microprocessor in a 0.12-μm L/sub eff/ CMOS technology with copper interconnects

Abstract

This paper describes the performance improvements of a reduced instruction set computer (RISC) microprocessor that has migrated from a 2.5 V technology to a 1.8 V technology. The 1.8 V technology implements copper interconnects and low V/sub t/ field-effect transistors in speed-critical paths and has an L/sub eff/ of 0.12 /spl mu/m. Global clock latency and skew are improved by using copper wires, and early mode timings are improved by reducing clock skew and adding buffers. These enhancements, along with an environment of 2.0 V, 85/spl deg/C, and with a fast process, produced a 480-MHz RISC microprocessor.