2005 · 45 citations · 12 references
EngineeringElectrical EngineeringMicroelectronicsVlsi DesignCmos Circuit DesignIntegrated Circuit DesignPhysical DesignGate Oxide Thickness EffectsProtectionProtection Circuits
ESD robustness of 4 kV HBM is achieved in CMOS-on-SOI ESD protection networks in an advanced sub-0.25 /spl mu/m CMOS-on-SOI technology. Design layout, body contact, floating gate effects and novel ESD protection implementations are discussed.
12
Low-power design: ways to approach the limits
Eric A. Vittoz · 2002 · 224 citations
Engineering, Computer Engineering, Electrical Engineering +14
Low-voltage CMOS device scaling
Chenming Hu · 2002 · 43 citations
Engineering, Computer Engineering, Electrical Engineering +14