C. Surisetty

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

Ruijie Xie, P. Montanini, Kerem Akarvardar et al. · 2016 · 139 citations

Engineering, Electron-beam Lithography, Finfet Technology +18

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

Kwangyou Seo, Bala Haran, Divya Gupta et al. · 2014 · 97 citations

Engineering, Vlsi Design, Finfet Technology +18

Tungsten and cobalt metallization: A material study for MOL local interconnects

V. Kamineni, M. Raymond, S. Siddiqui et al. · 2016 · 63 citations

Mol Local Interconnects, Engineering, Cvd W-based Metallization +21

Cleaning Solutions for Ultrathin Co Barriers for Advanced Technology Nodes

S. R. Alety, Uma Rames Krishna Lagudu, R. Popuri et al. · ECS Journal of Solid State Science and Technology · 2017 · 29 citations

Materials Science, Chemical Engineering, Corrosion Protection +15

Air spacer for 10nm FinFET CMOS and beyond

Kangguo Cheng, C. Surisetty, Raja Muthinti et al. · 2016 · 26 citations

Low-power Electronics, Electrical Engineering, Finfet Cmos +14