Y. Tagawa

Direct Evaluation of Gate Line Edge Roughness Impact on Extension Profiles in Sub-50-nm n-MOSFETs

H. Fukutome, Y. Momiyama, T. Kubo et al. · IEEE Transactions on Electron Devices · 2006 · 41 citations

Engineering, Electrical Engineering, Materials Science +17

Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs

Ken Goto, Shuichi Satoh, Hiromichi Ohta et al. · 2005 · 31 citations

Engineering, Electrical Engineering, Materials Science +17

Novel Channel-Stress Enhancement Technology with eSiGe S/D and Recessed Channel on Damascene Gate Process

J. Wang, Y. Tateshita, Shuji Yamakawa et al. · 2007 · 27 citations

Engineering, Electrical Engineering, Electronic Materials +11

High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates

Y. Tateshita, J. Wang, K. Nagano et al. · 2006 · 25 citations

Engineering, Electrical Engineering, Materials Science +17

High performance 25 nm gate CMOSFETs for 65 nm node high speed MPUs

Kenichi Gotō, Y. Tagawa, Hiromichi Ohta et al. · 2004 · 22 citations

Engineering, Electrical Engineering, Electronic Materials +16