Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs

Abstract

Strain enhancing laminated SiN (SELS) is reported for the first time. Although the same thickness and stress SiN film is used, channel strain is enhanced by multi layer deposition. This effect was investigated by our simulations and experiments. To solve wafer bending problem, we developed a new process flow which selectively forms SELS only on the nMOS gate. A high performance 37nm gate nMOSFET and 45nm gate pMOSFET (stage IV) were demonstrated with a drive currents of 1120/spl mu/A//spl mu/m and 690/spl mu/A//spl mu/m at V/sub dd/=1V/I/sub off/=100nA//spl mu/m, respectively. This is the best drive current among the recent reports.