Y. Shimamune

45nm CMOS technology with low temperature selective epitaxy of SiGe

Naoyoshi Tamura, Y. Shimamune · Applied Surface Science · 2008 · 34 citations

Electrical Engineering, Engineering, Rf Semiconductor +7

Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs

Ken Goto, Shuichi Satoh, Hiromichi Ohta et al. · 2005 · 31 citations

Materials Engineering, Electrical Engineering, Technology Booster +13

High performance 30 nm gate bulk CMOS for 45 nm node with σ-shaped SiGe-SD

Hiromichi Ohta, Y. Kim, Y. Shimamune et al. · 2006 · 26 citations

Electrical Engineering, Engineering, Vlsi Design +15

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

T. Miyashita, Keiji Ikeda, Y. S. Kim et al. · 2007 · 22 citations

Engineering, Vlsi Design, Emerging Memory Technology +18

Junction Profile Engineering with a Novel Multiple Laser Spike Annealing Scheme for 45-nm Node High Performance and Low Leakage CMOS Technology

Tsuyoshi Yamamoto, T. Kubo, T. Sukegawa et al. · 2007 · 21 citations

Engineering, Vlsi Design, Optoelectronic Devices +17