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High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology
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2007
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Unknown Venue
EngineeringVlsi DesignEmerging Memory TechnologyComputer ArchitectureIntegrated CircuitsInterconnect (Integrated Circuits)Highly Enhanced StrainAdvanced Packaging (Semiconductors)NanoelectronicsLayout DependenceAggressively-scaled High-performanceHigh-epsilon Offset SpacerElectronic Packaging45-Nm Cmos TechnologyFull-porous Low-k Interconnects3D Ic ArchitectureElectrical EngineeringComputer EngineeringMicroelectronicsLow-power ElectronicsBeyond Cmos
We present an aggressively-scaled high-performance and low-power bulk CMOS platform technology aiming at large-scale (multi-core) high-end use with 45-nm ground rule. By utilizing a high-epsilon offset spacer and FET specific multiple-stressors with highly enhanced strain, world competitive high performance NFET and PFET drive currents of 1.22/0.765 mA/mum at 100 nA/mum off-current, and 0.97/0.63 mA/mum at 10 nA/mum off-current at |Vd|= 1V, respectively, were obtained with minimizing layout dependence. This technology also offers a functional high density SRAM with a much smaller cell, i.e., 0.255 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . In addition, full- porous low-k (k = 2.25) BEOL integration lowers RC delay and reduces total circuit delay by 25% at the long wiring region compared to that of our previous technology.