M. Harmes

Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology

P. Morrow, Choon-Ho Park, Shriram Ramanathan et al. · IEEE Electron Device Letters · 2006 · 167 citations

Engineering, Computer Engineering, Electrical Engineering +17

Experimental validation of crosstalk simulations for on-chip interconnects using S-parameters

M. Kobrinsky, S. Chakravarty, Dan Jiao et al. · IEEE Transactions on Advanced Packaging · 2005 · 39 citations

Engineering, Computer Engineering, Electrical Engineering +17

A novel technique for full-wave modeling of large-scale three-dimensional high-speed on/off-chip interconnect structures

Dan Jiao, Md. Mohiuddin Mazumder, S. Chakravarty et al. · 2003 · 36 citations

Engineering, Computational Engineering, Electrical Engineering +17

Resistance and electromigration performance of 6 nm wires

J. S. Chawla, Seung-Hun Sung, Stephanie A. Bojarski et al. · 2016 · 30 citations

Engineering, Electrical Engineering, Materials Science +17

Demonstration of a reliable high-performance and yielding Air gap interconnect process

Hui Jae Yoo, S. Balakrishnan, Jeff Bielefeld et al. · 2010 · 22 citations

Engineering, Computer Engineering, Electrical Engineering +13