Ji-Jan Chen

A built-in self-test scheme for the post-bond test of TSVs in 3D ICs

Yu-Jen Huang, Jin-Fu Li, Ji-Jan Chen et al. · 2011 · 72 citations

Bist Scheme, Engineering, Vlsi Design +21

DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks

Sergej Deutsch, Brion Keller, Vivek Chickermane et al. · 2012 · 38 citations

Engineering, Vlsi Design, Mem Testing +18

Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits

Pei-Wen Luo, Jwu-E Chen, Chin‐Long Wey et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2008 · 38 citations

Electrical Engineering, Engineering, Vlsi Design +13

Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study

Sandeep Goel, Saman Adham, Min-Jer Wang et al. · 2013 · 34 citations

Engineering, Vlsi Design, Dft Architecture +20

A Test Integration Methodology for 3D Integrated Circuits

Che-Wei Chou, Jin-Fu Li, Ji-Jan Chen et al. · 2010 · 31 citations

Engineering, Computer Architecture, Computer-aided Design +20