Min-Jer Wang

3D-IC interconnect test, diagnosis, and repair

Chun‐Chuan Chi, Cheng‐Wen Wu, Min-Jer Wang et al. · 2013 · 41 citations

3D-ic Yield, 3D Ic Architecture, Electrical Engineering +13

Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study

Sandeep Goel, Saman Adham, Min-Jer Wang et al. · 2013 · 34 citations

Engineering, Vlsi Design, Dft Architecture +20

A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS

S. Romanovsky, A. Katoch, Arun Achyuthan et al. · 2008 · 26 citations

Non-volatile Memory, Engineering, Memory Design +20

A memory yield improvement scheme combining built-in self-repair and error correction codes

Tze-Hsin Wu, Po‐Yuan Chen, Mincent Lee et al. · 2012 · 24 citations

Hardware Security, Reliability Engineering, Eemr Scheme +15

Heterogeneous Power Delivery for 7nm High-Performance Chiplet-Based Processors using Integrated Passive Device and In-Package Voltage Regulator

Alan Roth, Charlie Zhou, Mei Wong et al. · 2020 · 17 citations

Engineering, Computer Architecture, Integrated Circuits +17