Heterogeneous Power Delivery for 7nm High-Performance Chiplet-Based Processors using Integrated Passive Device and In-Package Voltage Regulator

Abstract

We demonstrate two heterogeneous solutions to improve power delivery to High-Performance Computing (HPC) processors. The scalable HPC vehicle integrates two 7nm CMOS processor chiplets, each with four ARM¯ Cortex¯-A72 cores, that are mounted on a Chip-on-Wafer-on-Substrate (CoWoS¯) silicon interposer [1]. In the first solution, Integrated Passive Device (IPD) capacitors are placed directly beneath the interposer to provide more accessible and effective supply noise decoupling. The result is 3.9% higher maximum clock frequency at a core supply of 1.135V. In the second solution, the processor is powered by a laterally mounted in-Package Voltage Regulator (PVR) built in 28nm CMOS augmented with high-permeability on-die inductors. The processor performance provided by the buck converter-based PVR matches that by an off-package External Voltage Regulator (EVR). As processor power increases with higher core counts, PVRs with on-die inductors will be increasingly compelling for efficient system power delivery.