Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits

TLDR

Process variations cause spatially correlated changes in device parameters, and because analog performance depends on accurate capacitance ratios, parallel unit capacitances help reduce mismatch. This paper investigates how capacitance correlation affects yield improvement in mixed‑signal/analog integrated circuits. The authors express capacitance‑ratio mismatch and variation as functions of capacitance correlation, incorporating process variation and device mismatch early in design to lower costs and accelerate time to market. Early consideration of process variation and device mismatch reduces design costs and speeds time to market.

Abstract

Random fluctuations in process conditions change the physical properties of parameters on a chip. The correlation of device parameters depends on spatial locations. In general, the closer devices most likely have the similar parameter variation. The key performance of many analog circuits is directly related to accurate capacitance ratios. Parallel unit capacitances have a great effect on reducing ratio mismatch. This paper addresses the impact of capacitance correlation on the yield enhancement of mixed-signal/analog integrated circuits. The relationship between correlation and variation of capacitance ratio is also presented. Therefore, both mismatch and variation of capacitance ratio can be expressed in terms of capacitance correlation. Furthermore, both process variation and device mismatch are considered in the early design phase to reduce the design costs and speed up the time to market.