Naveen Kakarla

Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node

Rongmei Chen, Giuliano Sisto, Anne Jourdain et al. · 2021 IEEE International Electron Devices Meeting (IEDM) · 2021 · 24 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +17

Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era

Giuliano Sisto, Odysseas Zografos, Bilal Chehab et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2022 · 22 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +17

Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node

Rongmei Chen, Giuliano Sisto, Michele Stucchi et al. · 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 2022 · 22 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +15

Design enablement of CFET devices for sub-2nm CMOS nodes

Odysseas Zografos, Bilal Chehab, P. Schuddinck et al. · 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) · 2022 · 13 citations

Engineering, Computer Engineering, Electrical Engineering +16