Deleep R. Nair - Concepedia

Author

Deleep R. Nair

Indian Institute of Technology Madras ORCID

Also Known As

D. Nair, D. R. Nair, D.R. Nair, Deleep Nair, Deleep R Nair, Deleep R. Nair, Nair, D., Nair, Deleep R

Publications

718

Citations

H-Index

Concepts

All Affiliations

Indian Institute of Technology Madras IBM (United States)STMicroelectronics (United States)Toshiba (United States)Infineon Technologies (Germany)

About

Deleep R. Nair is an author at Indian Institute of Technology Madras specializing in microelectronics, engineering, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	14	18	582
2	Electrical Engineering	14	18	582
3	Applied Physics	12	12	443
4	Computer Engineering	7	7	375
5	Industrial Engineering	1	1	28

Deleep R. Nair

Publications

582

Citations

H-Index

Page 1

	Year	Citations
A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process X. Chen, S. Samavedam, Vijay Narayanan, Low-power ElectronicsLow Power ApplicationsElectrical EngineeringEngineeringVlsi Design	2008	112
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications Siddarth Krishnan, U. Kwon, N. Moumen, Sige ChannelsLow Power ApplicationsEngineeringVlsi DesignIntegrated Circuits	2011	81
32nm general purpose bulk CMOS technology for high performance applications at low voltage F. Arnaud, J. Liu, Yong Meng Lee, Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignHigh-frequency Device	2008	56
Scaling of 32nm low power SRAM with high-K metal gate Haining Yang, Robert Wong, R. Hasumi, Electrical EngineeringEngineeringVlsi DesignPhysicsTechnology Scaling	2008	49
Competitive and cost effective high-k based 28nm CMOS technology for low power applications F. Arnaud, Aaron Thean, M. Eller, Low-power ElectronicsLow Power ApplicationsElectrical EngineeringLow PowerEngineering	2009	43
Drain disturb during CHISEL programming of NOR flash EEPROMs-physical mechanisms and impact of technological parameters Deleep R. Nair, Souvik Mahapatra, S. Shukuri, IEEE Transactions on Electron Devices Materials EngineeringDevice ModelingElectrical EngineeringSemiconductor DeviceEngineering	2004	28
Realization of preferential (100) oriented AlN thin films on Mo coated Si substrate using reactive RF magnetron sputtering A. K. Das, Martando Rath, Deleep R. Nair, Applied Surface Science Materials EngineeringMaterials ScienceElectrical EngineeringSi SubstrateEngineering	2021	26
Analysis of Gate-Induced Drain Leakage Mechanisms in Silicon-Germanium Channel pFET Vishal A. Tiwari, D. Jaeger, A. Scholze, IEEE Transactions on Electron Devices Device ModelingElectrical EngineeringEngineeringPhysicsSubstrate Bias	2014	23
Piezoelectric-on-Silicon Array Resonators With Asymmetric Phononic Crystal Tethering Udit Rawat, Deleep R. Nair, Amitava DasGupta Journal of Microelectromechanical Systems Electrical EngineeringVibrationsEngineeringHigh-frequency DeviceAcoustic Metamaterial	2017	23
A Scalable, Broadband, and Physics-Based Model for On-Chip Rectangular Spiral Inductors Sathya Sree Jayaraman, Venkata Narayana Rao Vanukuru, Deleep R. Nair, IEEE Transactions on Magnetics Electrical EngineeringPhysical Design (Electronics)EngineeringNonlinear CircuitHigh-frequency Device	2019	22

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