Competitive and cost effective high-k based 28nm CMOS technology for low power applications

Abstract

In this paper, we present a cost-effective 28 nm CMOS technology for low power (LP) applications based on a high-k, single-metal-gate-first architecture. We report raw gate densities up to 4200 kGate/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and, using the ARM Cortex-R4F as a reference, we report achievement of an overall 2.4x area reduction in 28 nm from 45 nm technology. Our high-density SRAM bit-cell (area= 0.120mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) has a demonstrated Static Noise Margin (SNM) of 213 mV at 1 V. Fully compatible with power/leakage management techniques intensively used in low power designs, the transistor drive currents are increased +35% & +10%, for nFET and pFET respectively, with respect to a 28 nm LP poly/SiON reference. Compatible with LP system-on-chip requirements, ultra low-cost, high performance analog devices are reported which leverage a dramatic improvement in matching factor (AVT~2mV.um) versus our previously-reported result. An optimized interconnection scheme based on Extreme Low k (ELK) dielectric (k~2.4) and advanced metallization allows high density wiring with competitive R-C versus our previous technology.