M. Zaleski

A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

X. Chen, S. Samavedam, Vijay Narayanan et al. · 2008 · 113 citations

Engineering, Computer Engineering, Electrical Engineering +16

32nm general purpose bulk CMOS technology for high performance applications at low voltage

F. Arnaud, J. Liu, Yong Meng Lee et al. · 2008 · 56 citations

Engineering, Computer Engineering, Electrical Engineering +17

High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm 2 SRAM and ultra low-k back end with eleven levels of copper

B. Greene, Qingqing Liang, K. Amarnath et al. · Symposium on VLSI Technology · 2006 · 40 citations

Engineering, Computer Engineering, Electrical Engineering +15

A Cost-Effective Low Power Platform for the 45-nm Technology Node

E. Josse, S. Parihar, Olivier Callen et al. · 2006 · 33 citations

Engineering, Computer Engineering, Electrical Engineering +11

Challenges of analog and I/O scaling in 10nm SoC technology and beyond

A. Wei, Jagar Singh, G. Bouche et al. · 2014 · 17 citations

Engineering, Electrical Engineering, Materials Science +17