T. Noguchi

A 15-ns 32*32-b CMOS multiplier with an improved parallel structure

M. Nagamatsu, S. Tanaka, J. Mori et al. · IEEE Journal of Solid-State Circuits · 1990 · 88 citations

Engineering, Computer Engineering, Electrical Engineering +16

Mobility improvement for 45nm node by combination of optimized stress control and channel orientation design

T. Komoda, A. Oishi, T. Sanuki et al. · 2005 · 42 citations

Engineering, Electrical Engineering, Microelectronics +12

Measurement of three dimensional stress and modeling of stress induced migration failure in aluminium interconnects

A. Tezaki, T. Mineta, H. Egawa et al. · 2002 · 37 citations

Engineering, Materials Engineering, Materials Science +17

Scalability of strained silicon CMOSFET and high drive current enhancement in the 40 nm gate length technology

T. Sanuki, A. Oishi, Y. Morimasa et al. · 2004 · 35 citations

Engineering, Electrical Engineering, Microelectronics +16

65 nm CMOS technology (CMOS5) with high density embedded memories for broadband microprocessor applications

N. Yanagiya, Shôichi Matsuda, S. Inaba et al. · 2003 · 23 citations

Engineering, Computer Engineering, Electrical Engineering +17